HyperParser: A High-Performance Parser Architecture for Next Generation Programmable Switch and SmartNIC

Abstract

Programmable switches and SmartNICs motivate the programmable network. ASIC is adopted in programmable switches to achieve high throughput, and FPGA-based SmartNIC is becoming increasingly popular. The programmable parser is a key element in programmable switches and SmartNICs, which can identify the protocol types and extract the relevant fields. The programmable parser for the next generation programmable switches and SmartNICs requires a significant improvement in PPAL (performance, power, area, and latency), which is quite challenging. According to the Ethernet roadmap, 800 Gbps and 1.6 Tbps are expected to be the future switch interface speeds after 2022, which leads to higher throughput of the parser. Meanwhile, the end of Dennard scaling and the slowdown of Moore’s Law result in limited power and area. Besides, the need for low-latency and low-jitter operations at the datacenter scale continues to grow. Aforementioned requirements on PPAL inspire us to propose HyperParser, a high-performance parser architecture for next generation programmable switches and FPGA-based SmartNICs. The key innovation of HyperParser is the adoption of the butterfly network, which is widely used in cryptographic circuits. HyperParser supports ASIC and FPGA implementations, with low and deterministic latency. The PPAL of the ASIC implementation are 3.2-6.8 Tbps, 0.55 W, 2M gates, and 11.7 ns, and the PPAL of the FPGA implementation are 1.3-2.8 Tbps, 16.2 W, 43K LUTs, and 40 ns. The source code of HyperParser has been released on Github.