Hardware implementation of ISODATA and Otsu thresholding algorithms

Abstract

Image and video processing algorithms implemented in software, require most computation time when the image size is increased. Also, some algorithms must be processed at high-speed, for example the image thresholding algorithms for high throughput real-time applications. Then, in order to overcome this requirement, the algorithms must be efficiently implemented in hardware. In this paper, we present the hardware architectures for ISODATA and Otsu thresholding algorithms comparing area, latency, throughput and power consumption. The designs are described using generic structural VHDL and synthesized on the FPGA EP4CE115F29C7N. The designed architectures were verified using Signal Tap and an image acquisition system based on the D5M camera and the DE2-115 development kit of Terasic.