A 24Gb/s/pin 8Gb GDDR6 with a Half-Rate Daisy-Chain-Based Clocking Architecture and IO Circuitry for Low-Noise Operation

2021 IEEE International Solid- State Circuits Conference (ISSCC) Pub Date : 2021-02-13 DOI:10.1109/ISSCC42613.2021.9365844

Kyunghoon Kim, Joo-Hyung Chae, Jaehyeok Yang, Ji-Hyo Kang, Gang-Sik Lee, Sangyeon Byeon, Youngtaek Kim, Boram Kim, Donghoon Kim, Yeongmuk Cho, Kangmoo Choi, Hye-Lim Park, Junghwan Ji, S. Jeong, Yongsuk Joo, Jaehoon Cha, Mi-Lim Park, Hongdeuk Kim, Sijun Park, K. Kong, Sunho Kim, Sangkwon Lee, J. Chun, Hyung-Seuk Kim, S. Cha

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引用次数: 4

Abstract

The demand for high-performance graphics systems used for artificial intelligence continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. Enabling GDDR6 DRAM to achieve data rates beyond 18Gb/s/pin [1] requires identifying and solving factors that affect the speed of a memory interface. Prior studies have showed that the memory interface is vulnerable from the signal integrity (SI) and power integrity (PI) perspective, since it is based on a parallel interface using single-ended signaling. Furthermore, circuit schemes to mitigate process, voltage, and temperature (PVT) variations in sub-nanometer DRAM process are required to improve performance. To achieve 24Gb/s/pin on a 1.35V DRAM process, this work proposes a GDDR6 DRAM with a half-rate clocking architecture and optimized I/O.

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24Gb/s/引脚8Gb GDDR6，半速率菊花链时钟架构和低噪声操作IO电路

对用于人工智能的高性能图形系统的需求持续增长;这种趋势要求图形系统实现更高的带宽。要使GDDR6 DRAM实现超过18Gb/s/pin的数据速率[1]，需要识别和解决影响内存接口速度的因素。先前的研究表明，从信号完整性(SI)和功率完整性(PI)的角度来看，存储接口是脆弱的，因为它是基于使用单端信令的并行接口。此外，为了提高性能，需要在亚纳米DRAM工艺中减小工艺、电压和温度(PVT)变化的电路方案。为了在1.35V DRAM上实现24Gb/s/pin，本工作提出了一种具有半速率时钟架构和优化I/O的GDDR6 DRAM。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2021 IEEE International Solid- State Circuits Conference (ISSCC)

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