A partitioning approach to design fault-tolerant arithmetic arrays

Abstract

An alternative fault-tolerant design in VLSI-based arithmetic arrays using the partitioning technique is presented. The basic concept is that the arithmetic array can be divided into m parts and its operation can be completed through m iterative calculations with some one part. By taking three such parts with a majority-voting technique at each iteration, error correction can be achieved through m-step computations. This leads to the same fault tolerance capability as triple modular redundancy (TMR). The overheads of chip area and operation time are only introduced by multiplexers, latches, and voters and can be reduced by selecting an appropriate value of m. Based on the AT/sup 2/ (where A is the chip area and T is the operation time) measure of VLSI performance, the proposed design is shown to be superior to the general TMR method. Some application-specified tradeoffs between speed performance and area cost are also presented.<>