Accelerating FPGA-based object detection via a visual information extraction cascade

Abstract

Object detection is a major step in several computer vision applications. Recent advances in hardware acceleration for real-time object detection feature extensive use of reconfigurable hardware fabric (Field Programmable Gate Arrays -- FPGAs), and relevant research has produce quite fascinating results, in both accuracy of the detection algorithm, as well as the performance in terms of frames per second (FPS) for use in embedded systems. Detecting objects in images however, is a daunting task, and involves steps which are hardware- inefficient, both in terms of the datapath design and in terms of input/output and memory accesses. In this work, we present how a visual information extraction cascade composed of disparity estimation, edge detection and motion detection, can help in significantly reducing the data that needs to be computed. As such, it can reduce the power consumption while improving the performance of object detection algorithms. Initial results indicate data search reduction of up to 87% in the best case, with an average of more than 50%.