{"title":"Access Pattern Based Re-reference Interval Table for Last Level Cache","authors":"B. Yu, Yifan Hu, Jianliang Ma, Tianzhou Chen","doi":"10.1109/PDCAT.2011.13","DOIUrl":null,"url":null,"abstract":"The memory access stream to the last level cache (LLC) is a filtered version from the upper level caches. There are a large number of cache blocks with long re-reference interval in the LLC. What's worse, zero reuse blocks are in abundance in the LLC and pollute the LLC for a long time. Access pattern based re-reference interval table (RRIT), here we propose, is an efficient management technology for the LLC. RRIT introduces a table to track consecutive blocks' re-reference interval. And then predicts the re-reference interval for a new incoming block. RRIT always selects the block with the max re-reference interval as the victim block when a cache replacement issue occurs. Furthermore, we propose a dead block filtering (RRIT-Filter) mechanism based on RRIT. RRIT-Filter bypasses the predicted dead block and improves LLC efficiency. Our evaluations using the SPEC2006 workloads on a single-core with a 2MB LLC show that RRIT and RRIT-Filter outperform LRU replacement on the throughput metric by an average of 6.6% and 8.6% respectively. Our evaluations with 10 multi-programmed workloads on a 4-core CMP with an 8MB shared LLC show that our strategy outperforms LRU replacement on the throughput metric by an average of 23% and 39% respectively.","PeriodicalId":137617,"journal":{"name":"2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 12th International Conference on Parallel and Distributed Computing, Applications and Technologies","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PDCAT.2011.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The memory access stream to the last level cache (LLC) is a filtered version from the upper level caches. There are a large number of cache blocks with long re-reference interval in the LLC. What's worse, zero reuse blocks are in abundance in the LLC and pollute the LLC for a long time. Access pattern based re-reference interval table (RRIT), here we propose, is an efficient management technology for the LLC. RRIT introduces a table to track consecutive blocks' re-reference interval. And then predicts the re-reference interval for a new incoming block. RRIT always selects the block with the max re-reference interval as the victim block when a cache replacement issue occurs. Furthermore, we propose a dead block filtering (RRIT-Filter) mechanism based on RRIT. RRIT-Filter bypasses the predicted dead block and improves LLC efficiency. Our evaluations using the SPEC2006 workloads on a single-core with a 2MB LLC show that RRIT and RRIT-Filter outperform LRU replacement on the throughput metric by an average of 6.6% and 8.6% respectively. Our evaluations with 10 multi-programmed workloads on a 4-core CMP with an 8MB shared LLC show that our strategy outperforms LRU replacement on the throughput metric by an average of 23% and 39% respectively.