Fault Diagnosis Using Automatic Test Pattern Generation and Test Power Reduction Technique for VLSI Circuits

Ch. Narasimha Kumar, A. Madhumitha, N. S. Preetam, P. Gupta, J. P. Anita
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引用次数: 3

Abstract

As the complexity of the digital circuits increases there should be a check on its functionality in a more exhaustive way. So here comes the need for test pattern generation technique to detect the presence of the faults and to obtain the test patterns. The switching activity in digital circuits may overheat the circuit due to which unwanted responses may occur. This may lead to a high power consumption, so it is necessary to reduce the power. The proposed paper includes generation of test patterns and a technique for test power reduction in VLSI. The results have been validated using ISCAS’85 and ISCAS’89 benchmark circuits.
基于测试模式自动生成和测试功耗降低技术的VLSI电路故障诊断
随着数字电路复杂性的增加,应该以更详尽的方式对其功能进行检查。因此,需要测试模式生成技术来检测故障的存在并获得测试模式。数字电路中的开关活动可能使电路过热,从而可能发生不必要的响应。这可能会导致高功耗,因此有必要降低功率。本文主要介绍了VLSI测试模式的生成和测试功耗降低技术。使用ISCAS ' 85和ISCAS ' 89基准电路验证了结果。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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