{"title":"Fast Hardware Implementation of Renormalization for Context-based Adaptive Binary Arithmetic Coding","authors":"S. Wang, Zejie Kuang, Guohe Zhang, Li Sun","doi":"10.1109/ICIASE45644.2019.9074006","DOIUrl":null,"url":null,"abstract":"The promotion and application of HEVC face a great problem: how to reduce the coding complexity while ensuring the video compression rate. In order to reduce the complexity of renormalization, a fast renormalization algorithm is designed for the entropy coding module. This algorithm can perform renormalization and bit output without complex cyclic processes. At the meanwhile, an appropriate hardware structure is proposed and realized for the algorithm. Experimental results show that the design can reduce the renormalized frequency of 20.8%–25.6% and save the encoding time of 13.6%–30.9%. Moreover, the encoding rate can be up to 89 Mbin/s.","PeriodicalId":206741,"journal":{"name":"2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE International Conference of Intelligent Applied Systems on Engineering (ICIASE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIASE45644.2019.9074006","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The promotion and application of HEVC face a great problem: how to reduce the coding complexity while ensuring the video compression rate. In order to reduce the complexity of renormalization, a fast renormalization algorithm is designed for the entropy coding module. This algorithm can perform renormalization and bit output without complex cyclic processes. At the meanwhile, an appropriate hardware structure is proposed and realized for the algorithm. Experimental results show that the design can reduce the renormalized frequency of 20.8%–25.6% and save the encoding time of 13.6%–30.9%. Moreover, the encoding rate can be up to 89 Mbin/s.