An FPGA Decision Tree Classifier to Supervise a Communication SoC

Abdelrahman Elkanishy, Derrick T. Rivera, Abdel-Hameed A. Badawy, P. Furth, Z. Saifullah, Christopher P. Michael
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引用次数: 5

Abstract

Wireless communication protocols are used in all smart devices and systems. This work is part of a proposed supervisory circuit that classifies the operation of a communication SoC, in particular, a Bluetooth (BT) SoC, at a low sampling frequency by monitoring the RF output power and input supply current. In essence, the goal is to inexpensively fabricate an RF envelope detector, power supply current monitor, and classifier on a low-cost, low-frequency integrated circuit. When the supervisory circuit detects abnormal behavior, it can shut off power to the BT chip. We extract simple descriptive features from the input and output power signals. Then, we train a machine learning (ML) model to classify the different BT operation modes, such as advertising and transmit/receive modes. In this work, we implemented the ML classifier and feature extraction on an FPGA with 100% matching with the corresponding MATLAB code. In the experimental setup, which included a function generator and an on-board ADC, errors in the FPGA-sampled values degraded the match slightly to 99.26%. Finally, a low-power ASIC is synthesized from the Verilog code in $0.18-\mu \mathrm{m}$ CMOS, with an estimated area of 0.0152 mm2 and power of $9.43 \mu \mathrm{W}$.
基于FPGA的通信SoC决策树分类器
所有智能设备和系统都使用无线通信协议。这项工作是提出的监控电路的一部分,该电路通过监测射频输出功率和输入电源电流,对通信SoC(特别是蓝牙(BT) SoC)在低采样频率下的操作进行分类。从本质上讲,目标是在低成本,低频集成电路上廉价地制造射频包络检测器,电源电流监视器和分类器。当监控电路检测到异常行为时,可以切断BT芯片的电源。我们从输入和输出功率信号中提取简单的描述性特征。然后,我们训练了一个机器学习(ML)模型来分类不同的BT操作模式,如广告和发送/接收模式。在这项工作中,我们在FPGA上实现了机器学习分类器和特征提取,与相应的MATLAB代码100%匹配。在包含函数生成器和板载ADC的实验设置中,fpga采样值的误差略微降低了匹配度至99.26%。最后,利用Verilog代码在$0.18-\mu \mathrm{m}$ CMOS中合成了一个低功耗ASIC,估计面积为0.0152 mm2,功耗为$9.43 \mu \mathrm{W}$。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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