Simulation analysis of process-induced variability in nanoscale SOI and bulk FinFETs

Abstract

3D devices are prone to more complex sources of variability than conventional planar bulk and SOI MOSFETs. Corner simulations and statistical simulations are unique tools to understand the link between the device design and the circuit performance through accurate prediction of the variability. In this work we have demonstrated that SOI can efficiently help to reduce the process-induced FinFET variability, and hence improve the circuit performance. In particular, the better fin height control possible with SOI results in less variability in on-current. We have also established that SOI brings >;5% Isat improvement at identical Fin dimensions, thanks to the BOX isolation compared to the junction isolation depleting the bottom part of the bulk Fin.