A power management methodology for high-level synthesis

Abstract

In this paper, we present a power management technique targeted towards high-level synthesis of data-dominated behavioral descriptions. Our method is founded on the observation that variable assignment can significantly affect power management opportunities in the synthesized architecture. Based on this observation, we present a procedure for constraining variable assignment, so that the functional units in the synthesized architecture do not execute any spurious operations. Unlike many previously proposed power management techniques, our method does not have an attendant performance penalty. Experimental results indicate savings of up to 52.5% in power consumption over already power-optimized architectures, at area overheads not exceeding 6.4%.