{"title":"Low-power, folded cascode near rail-to-rail OTA for moderate frequency signal processing","authors":"Tripurari Sharan, Nipu Kumar Nath","doi":"10.1109/IESPC.2017.8071855","DOIUrl":null,"url":null,"abstract":"This paper presents a gate-driven, folded-cascode operational transconductance amplifier (FCOTA), operating in strong inversion region. The input core utilizes two complementary PMOS and NMOS input pairs to ensure rail-to-rail input common mode range (ICMR). The cascoded load structure at output port performs the job of current summer and provides enhanced gain due to high output impedance for FCOTA. The proposed OTA has been employed to implement universal biquadratic low-pass, high-pass, band-pass and notch transfer functions, simultaneously available at different nodes of the filter. The proposed FCOTA used dual supply voltage of ± 0.9V and dissipates around 93.6 μW power and provides 80.24 dB open loop gain and gain bandwidth (GBW) of 6.03 MHz. The Cadence VIRTUOSO environment using UMC 0.18 μm CMOS process technology has been used to simulate the proposed circuit.","PeriodicalId":383252,"journal":{"name":"2017 International Conference on Innovations in Electronics, Signal Processing and Communication (IESC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 International Conference on Innovations in Electronics, Signal Processing and Communication (IESC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IESPC.2017.8071855","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
Abstract
This paper presents a gate-driven, folded-cascode operational transconductance amplifier (FCOTA), operating in strong inversion region. The input core utilizes two complementary PMOS and NMOS input pairs to ensure rail-to-rail input common mode range (ICMR). The cascoded load structure at output port performs the job of current summer and provides enhanced gain due to high output impedance for FCOTA. The proposed OTA has been employed to implement universal biquadratic low-pass, high-pass, band-pass and notch transfer functions, simultaneously available at different nodes of the filter. The proposed FCOTA used dual supply voltage of ± 0.9V and dissipates around 93.6 μW power and provides 80.24 dB open loop gain and gain bandwidth (GBW) of 6.03 MHz. The Cadence VIRTUOSO environment using UMC 0.18 μm CMOS process technology has been used to simulate the proposed circuit.