Characteristics comparison of standard logic and HVCMOS processed SGLC embedded NVM

Abstract

The novel select gate lateral coupling (SGLC) cell has a single poly structure and operates using a lateral coupling between the floating gate (FG) and the select gate (SG) without additional processes on a base platform. In this paper, we have fabricated a pure logic CMOS processed SGLC cell for the first time and compared it with an HVCMOS processed SGLC cell. Because of the thinner gate oxide, the pure logic process fabricated SGLC cell has a lower coupling value than that of the HVCMOS process fabricated cell. However, the logic CMOS process fabricated cell shows a higher current performance than the HVCMOS process fabricated cell having a thicker gate oxide. Thanks to the inverse relationship between the coupling ratio and cell current, and the additional back bias effect, the logic CMOS processed cell gives comparable performance in terms of the programming speed, program-erase threshold voltage (VT) window and cell current. Both types of cells show more than 10 years of data retention lifetime at 85°C.