Review of Different Flip-Flop Circuits and a Modified Flip-Flop Circuit for Low Voltage Operation

V. Verma, D. A. K. M. Vaithivanathan, B. Kaur
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引用次数: 1

Abstract

In this paper, a less complex and single-phase clock flip-flop has been proposed. This flip-flop design is a modified version of the Novel Low-Complexity and Low-Power flip-flop. In the design of this flip-flop, a master-slave logic structure is used, representing a hybrid logic design consisting of both past transistor logic (PTL) and complementary metal-oxide-semiconductor (CMOS) logic. The proposed design comprises 15 transistors, two transistors less than the Low-complexity and low power flip-flop. The transistor reduction in this flip-flop is achieved by applying a logic structure reduction technique which also improves the power and timing performance of the design. The proposed plan is implemented on the 90 nm CMOS technology. The proposed plan is implemented on the 90 nm CMOS technology in Cadence Virtuoso tool. It is 48.13%, 30.94% and 22.71% of power saved as compared to TGFF, TCFF and LCLPFF respectively at 1 Volt power supply.
不同触发器电路的综述和一种改进的低电压触发器电路
本文提出了一种较简单的单相时钟触发器。该触发器设计是新型低复杂度和低功耗触发器的改进版本。在该触发器的设计中,使用了主从逻辑结构,代表了由过去晶体管逻辑(PTL)和互补金属氧化物半导体(CMOS)逻辑组成的混合逻辑设计。本设计由15个晶体管组成,比低复杂度低功耗触发器少2个晶体管。该触发器的晶体管缩减是通过应用逻辑结构缩减技术实现的,该技术还提高了设计的功率和时序性能。该方案在90纳米CMOS技术上实现。该方案在Cadence Virtuoso工具的90纳米CMOS技术上实现。在1伏电源下,与TGFF、TCFF和LCLPFF相比,分别节能48.13%、30.94%和22.71%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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