Parallel execution of the saturated reductions

Abstract

This paper addresses the problem of improving the execution performance of saturated reduction loops on fixed-point instruction-level parallel digital signal processors (DSPs). We first introduce "bit-exact" transformations, that are suitable for use in the ETSI and the ITU speech coding applications. We then present "approximate" transformations, the relative precision of which we are able to compare. Our main results rely on the properties of the saturated arithmetic.