Speculative ECC and LCIM Enabled NUMA Device Core

Abstract

Advanced process technology allows high memory density while securing high bandwidth. However, the increasing disparity between the computing unit and memory known as the memory wall impedes applications like artificial intelligence (AI) related workloads. The larger area of the memory cell introduces more memory defects, and this causes a memory yield problem. Error-correction code (ECC) is a widely used technique in modern computer architecture for system robustness. The overhead introduced by ECC limits the performance in certain timing-critical applications, like caches. The real time ECC combined with in-memory computation shows great power in addressing the performance and power bottlenecks. This paper proposes a hardware architecture to support memory ECC speculative computing cache. The paper presents a memory structure that implements separate data memory and tag memory, breaking the serialization between data access and error detection. The data is fetched making the prediction that tag is correct and uncorrupted. The system is rolled back when the prediction is wrong. Further optimization involves in-memory computing, which saves memory bandwidth. The proposed ECC speculative computing cache also reduced power and area overhead by reusing the logic from the computing cache.