HDL filter for optimized area-delay minimization in FPGA synthesis

Abstract

The quality of results (QoR) of FPGA synthesis operations is measured by two major criteria; area on chip, and circuit delay. In this paper we address the problem of minimizing the area and delay by filtering the input HDL descriptions to modify the constructs that are harmful to those criteria. A prototype tool was developed to make this filtering automatically, and the obtained results show the efficiency of this approach.