Timing distribution and data flow for the ATLAS Tile Calorimeter Phase II upgrade

Abstract

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at the Large Hadron Collider (LHC). The upgraded High Luminosity LHC will deliver five times the current nominal instantaneous luminosity. The ATLAS Phase II upgrade will upgrade the readout electronics of the TileCal for the HL-LHC. The majority of the front- and back-end electronics will be redesigned with a new readout strategy. In the upgraded readout architecture for Phase II, the frontend electronics consist of the Front-End Boards, Main Boards and the Daughter Boards. The Main Board digitizes the analog signals coming from the Front-End Boards (FEBs) connected to the PhotoMultiplier Tubes (PMTs), provides integrated data for minimum bias monitoring and includes electronics for PMT calibration. Three different FEB options with different signal acquisition strategies are under study: new 3-in-1 cards, QIE chip and FATALIC chip. The Daughter Board receives and distributes Detector Control System commands, clock and timing commands to the rest of the elements of the front-end electronics, as well as collects and transmits the digitized data to the backend electronics at the LHC frequency (~25 ns). In the back-end electronics, the TileCal PreProcessor (TilePPr) receives and stores the digitized data from the Daughter Boards in pipeline memories to cope with the latencies and rates specified in the new ATLAS DAQ architecture. The TilePPr interfaces between the data acquisition, trigger and control systems and the front-end electronics. In addition, the TilePPr distributes the clock and timing commands to the frontend electronics for synchronization with the LHC clock.