{"title":"A novel evolutionary algorithm for block-based neural network training","authors":"A. Niknam, P. Hoseini, B. Mashoufi, A. Khoei","doi":"10.1109/PRIA.2013.6528434","DOIUrl":null,"url":null,"abstract":"A novel evolutionary algorithm with fixed genetic parameters rate have presented for block-based neural network (BbNN) training. This algorithm can be used in BbNN training which faces complicated problems such as simulation of equations, classification of signals, image processing and implementation of logic gates and so on. The fixed structure of our specific BbNN allows us to implement the trained network by a fixed circuit rather than utilizing a reconfigurable hardware which is usually employed in conventional designs. Avoiding the reconfigurable hardware leads to lower power consumption and chip area. All simulations are performed in MATLAB software.","PeriodicalId":370476,"journal":{"name":"2013 First Iranian Conference on Pattern Recognition and Image Analysis (PRIA)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-03-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 First Iranian Conference on Pattern Recognition and Image Analysis (PRIA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PRIA.2013.6528434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A novel evolutionary algorithm with fixed genetic parameters rate have presented for block-based neural network (BbNN) training. This algorithm can be used in BbNN training which faces complicated problems such as simulation of equations, classification of signals, image processing and implementation of logic gates and so on. The fixed structure of our specific BbNN allows us to implement the trained network by a fixed circuit rather than utilizing a reconfigurable hardware which is usually employed in conventional designs. Avoiding the reconfigurable hardware leads to lower power consumption and chip area. All simulations are performed in MATLAB software.