A low-noise CMOS interface ASIC for capacitive MEMS accelerometer

Abstract

A low noise interface application-specific integrated circuit (ASIC) for capacitive accelerometer is presented in this paper. A low-noise low-offset charge integrator is proposed to improve performance of the system. Correlated double sampling, closed-loop operational mode and PID controller are employed in this circuit to minimize the noise, offset and improve stability of the system. Meanwhile, by adding self-test circuit, it improves the reliability of the system. The AISC is fabricated in 0.5μm two-poly two-metal CMOS process, it operates under ± 5V supply with a power dissipation of 40mW. The tested results have shown that the noise floor of the accelerometer is 9.8μg/Hz1/2, the sensitivity is 1.32V/g, nonlinearity is 0.06% and the bias stability is 0.129mg.