A 239-315 GHz CMOS Frequency Doubler Designed by Using a Small-Signal Harmonic Model

K. Takano, R. Dong, Sangyeop Lee, S. Amakawa, T. Yoshida, M. Fujishima
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引用次数: 2

Abstract

In order to realize a wideband frequency multiplier at terahertz frequencies, iterative optimization of circuit parameters is necessary. However, iterative execution of nonlinear simulation takes a prohibitively long time. We present a small-signal harmonic model, which is equivalent to using only the dominant components of a full set of X-parameters, to solve the problem. It is a simple but accurate nonlinear model suitable for obtaining the frequency response. A 300-GHz frequency doubler with an eight-stage driver amplifier is designed by using the technique. The frequency doubler is fabricated using a 40-nm CMOS process. It achieves a 3-dB bandwidth of 76 GHz from 239 to 315 GHz and a maximum output power of −10 dBm.
基于小信号谐波模型的239-315 GHz CMOS倍频器设计
为了实现太赫兹频率下的宽带倍频器,需要对电路参数进行迭代优化。然而,非线性仿真的迭代执行需要非常长的时间。我们提出了一个小信号谐波模型,它相当于只使用一组x参数的主导分量来解决这个问题。这是一个简单而准确的非线性模型,适合于获得频率响应。利用该技术设计了带8级驱动放大器的300ghz倍频器。该倍频器采用40纳米CMOS工艺制造。在239 ~ 315 GHz范围内实现76ghz的3db带宽,最大输出功率为−10dbm。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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