IP cores for hardware evolution of decision trees

Abstract

This paper proposes several IP cores for the hardware implementation of the complete decision tree inference algorithm. Evolving decision trees in hardware is motivated by the significant improvement in the evolution time compared to the time needed for software evolution. Several architectures for the hardware evolution of single oblique or nonlinear decision trees are presented. The proposed architectures are suitable for the implementation using both Field Programmable Gate Arrays (FPGA) and Application Specific Integrated Circuits (ASIC).