An Asymmetric, Energy Efficient One-to-Many Traffic-Aware Wireless Network-in-Package Interconnection Architecture for Multichip Systems

Abstract

High Performance Computing (HPC) platforms like blade servers consist of multiple processor chips which may be multicore CPUs, GPUs, memory modules and other subsystems. These high performance and memory intensive multichip systems require efficient support for one-to-many traffic patterns which originates from cache coherency, system-level synchronization mechanisms and other control signals. Small portions of such traffic can introduce congestion which significantly reduce overall performance and cause energy bottleneck unless low latency transmission is ensured by a one-to-many traffic aware interconnection architecture. Traditional metal based Network-on-Chip (NoC) interconnection architecture is not suitable for such traffic as it provides high-latency, power hungry multi-hop paths. To address this issue, we propose the design of a one-to-many traffic-aware Wireless Network-in-Package (WiNiP) architecture by introducing a novel asymmetric wireless interconnection topology and flow control. The proposed asymmetric topology provides low latency communication for one-to-many traffic and increase system bandwidth with lower energy consumption. Through cycle accurate simulator we show that the proposed topology reduce energy by 55.92% and outperforms other interconnection architecture for synthetic as well as application specific traffics.