Design and Analysis of High Speed RISC Processor Using Pipelining Technique

Abstract

RISC (Reduced Instruction Set Computer) is a programming style that focuses on simple, fundamental instructions that all take the same amount of time to execute. In this paper, we present a Verilog HDL-based 16-bit pipelined RISC processor. The processor incorporates ALU, Controller, Register File, Data Memory Unit blocks and13 instructions, making it extremely fast. The suggested RISC processor was tested on the Xilinx ISE platform.