{"title":"Fast symbol timing recovery techniques for burst-mode digital demodulators","authors":"N. D. Vo, T. Le-Ngoc","doi":"10.1109/VETECS.2003.1208864","DOIUrl":null,"url":null,"abstract":"A fast symbol timing recovery (STR) using feedforward maximum-likelihood estimation and interpolation for burst-mode broadband digital demodulator at the lowest sampling rate equivalent to twice the symbol rate. Both analysis and simulation are used to evaluate the performance of the proposed technique in an additive white Gaussian noise (AWGN) environment. The results show that the proposed scheme offers a very accurate and fast-convergence timing estimation suitable for communication systems using short preamble. The proposed scheme also has a simple structure that facilitates the implementation of low-complexity, and high-speed DSP circuitry.","PeriodicalId":272763,"journal":{"name":"The 57th IEEE Semiannual Vehicular Technology Conference, 2003. VTC 2003-Spring.","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-04-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 57th IEEE Semiannual Vehicular Technology Conference, 2003. VTC 2003-Spring.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VETECS.2003.1208864","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 7
Abstract
A fast symbol timing recovery (STR) using feedforward maximum-likelihood estimation and interpolation for burst-mode broadband digital demodulator at the lowest sampling rate equivalent to twice the symbol rate. Both analysis and simulation are used to evaluate the performance of the proposed technique in an additive white Gaussian noise (AWGN) environment. The results show that the proposed scheme offers a very accurate and fast-convergence timing estimation suitable for communication systems using short preamble. The proposed scheme also has a simple structure that facilitates the implementation of low-complexity, and high-speed DSP circuitry.