Vertical variants of PIN and p-NOI tunnel electronic devices and potential applications

Abstract

Communication traffic continue to improve due to the rapid growth in broadband access in recent years, frequently based on PIN or tunnel devices. The present paper discuses two kind of tunnel devices, in a vertical configuration through the cross-section, allowing the tunnel current flow from upper anode to bottom cathode: PIN and NOI device in a planar technology (p-NOI). Recently, the NOI — Nothing On Insulator device was proposed and timely updated. It belongs to a vacuum nano-transistor class. The simulations reveal few better device parameters versus related devices from literature. The vertical p-NOI device with a dual MOS gated diode configuration, overpass the fabricated vacuum nanotransistors with SS=0.4V/dec << SS=4.1V/dec. The PIN vertical diode with three compensated drift regions offers higher breakdown voltage, keeping the forward series resistance as low as possible. Finally, the applications of the PIN and NOI devices are presented.