Design of a hybrid reconfigurable coprocessor

Abstract

Reconfigurable processors are noticeable for their flexibility and high computation performance. Combining a general purpose processor with a reconfigurable coprocessor can improve the overall system performance. As wide range of algorithms have appeared due to the increasing complexity of applications, the general purpose processors undertake more serial computing tasks, which also leads to more time consumption during the task switching. Meanwhile, higher bandwidth demand comes with the increasing of computation efficiency. A hybrid reconfigurable coprocessor has been proposed here, which reduces its dependence on the general purpose processor. Optimized L2-cache has been designed to enhance the data locality and reusability. The proposed coprocessor based on an FPGA has been implemented which can operate at 100MHz. Experimental results show that much better performance has been achieved with this proposed coprocessor.