A Sub-1 ppm/°C CMOS Bandgap Voltage Reference With Process Tolerant Piecewise Second-Order Curvature Compensation

Yongjoon Ahn, Suhwan Kim, Hyunjoong Lee
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引用次数: 2

Abstract

This paper presents a CMOS high-precision bandgap voltage reference. To obtain low temperature coefficient (TC) regardless of process variation, piecewise second-order curvature compensation method is proposed. Curvature compensation current is generated through current subtraction and current squaring operation with two currents with different dependence on temperature. Also, several circuit techniques are adopted to achieve compensate error sources. Chopping technique is utilized to cancel 1/f noise and DC offset of the error amplifier. Trimming resistor is used to compensate process variation. The bandgap reference is designed in a 0.13µm CMOS process. Post layout simulation shows that TC of the bandgap reference is 0.64ppm/°C over a wide temperature range of -40°C to 125°C. Moreover, sub-1 ppm/°C TC is achieved irrespective of process variation after two-point temperature trimming. The bandgap reference consumes 44µA at 27°C and layout size is 0.0534mm2.
具有制程容错分段二阶曲率补偿的低于1 ppm/°C的CMOS带隙电压基准
本文提出了一种CMOS高精度带隙电压基准电路。为了获得不受工艺变化影响的低温系数,提出了分段二阶曲率补偿方法。曲率补偿电流是通过电流减法和电流平方运算产生的,两种电流对温度的依赖程度不同。同时,采用多种电路技术实现误差源的补偿。利用斩波技术消除误差放大器的1/f噪声和直流偏置。微调电阻用于补偿工艺变化。带隙基准采用0.13µm CMOS工艺设计。后布局仿真表明,在-40°C至125°C的宽温度范围内,带隙基准的TC为0.64ppm/°C。此外,在两点温度修剪后,无论工艺变化如何,都可以实现低于1 ppm/°C的TC。在27°C时,带隙基准功耗为44µA,布局尺寸为0.0534mm2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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