Impact analysis of stochastic transistor aging on current-steering DACs in 32nm CMOS

Abstract

Advanced CMOS technology introduces reliability challenges that are no longer fully resolved at the technology level. This paper studies the impact of transistor degradation at the circuit level. Particular attention is paid to the change in matching characteristics. This mismatch is critical for the performance of a lot of analog circuits such as current-steering DACs. A ‘design for reliability’ technique using higher-than-nominal supply voltage allows increased performance and lower area usage at the expense of increased degradation. A ‘Switching-Sequence Post Adjustment’ (SSPA) digital calibration method is used to reduce the area even more, but can also provide a ‘dynamic resequencing’, which ensures reliable operation of the circuit at all times. A 10-bit DAC is analysed using 32nm data. A degradation-induced accuracy decrease of 0.33 bit, of which 0.21 bit can be compensated using the SSPA algorithm, is observed, yielding a factor 25 area reduction.