V. Putcha, Marko Simicic, P. Weckx, B. Parvais, J. Franco, B. Kaczer, D. Linten, D. Verkest, A. Thean, G. Groeseneken
{"title":"Smart-array for pipelined BTI characterization","authors":"V. Putcha, Marko Simicic, P. Weckx, B. Parvais, J. Franco, B. Kaczer, D. Linten, D. Verkest, A. Thean, G. Groeseneken","doi":"10.1109/IIRW.2015.7437076","DOIUrl":null,"url":null,"abstract":"Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.","PeriodicalId":120239,"journal":{"name":"2015 IEEE International Integrated Reliability Workshop (IIRW)","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Integrated Reliability Workshop (IIRW)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IIRW.2015.7437076","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Deeply-scaled transistors fabricated in advanced High-k/Metal Gate (HK/MG) technologies have an intrinsic variability, requiring characterization of a large number of transistors to obtain statistically relevant data. A powerful tool in the form of a Smart-array circuit is designed to serve the BTI characterization needs on an industrial scale, where time plays an important role. The Smart-array circuit is designed such that 700 pMOS and nMOS transistors can be measured using the concept of pipelining. A significant reduction of up to 88.5% in time is demonstrated by establishing a pipeline of 15 pMOS transistors and the Measure-Stress-Measure (MSM) scheme of choice.