On-chip cache memory resilience

Abstract

This paper investigates the system-level impact of soft errors occurring in cache memory and proposes a novel cache-memory design approach for improving the soft-error resilience. Radiation experiments are conducted to quantify the severity of errors attributed to transients occurring in a cache memory subsystem. Simulation-based fault injections are then conducted to determine major failure modes and to assess the cost/benefits in cache memory designs/configuration alternatives. The performance, reliability, and overhead for each design configuration, e.g., cache block-size and write policy, are studied. The results indicate that the performance enhancement approaches using large cache block-sizes can adversely affect the soft-error sensitivity of the system. Write-through cache design is more susceptible to incomplete/incorrect program termination, while write-back cache design is more prone to data corruptions. A resilient cache design scheme, selective set invalidation (SSI), that better scrubs the cache-memory errors is proposed and evaluated.