A 40-Gb/s/pin Low-Voltage POD Single-Ended PAM-4 Transceiver with Timing Calibrated Reset-less Slicer and Bidirectional T-Coil for GDDR7 Application

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) Pub Date : 2022-06-12 DOI:10.1109/vlsitechnologyandcir46769.2022.9830507

Hyunsub Norbert Rie, Chang-Soo Yoon, J. Byun, Sucheol Lee, Garam Kim, J. Kim, Junyoung Park, Hyunyoon Cho, Youngdo Um, Hyungmin Jin, Kwangseob Shin, M. Jung, Gou Cha, Minjae Lee, Youngmin Kim, Byeori Han, Yuseong Jeon, Ji-Sang Lee, E. Shin, Hyuk-Jun Kwon, Youngdon Choi, J. Choi, Hyungjong Ko

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引用次数: 2

Abstract

This paper presents a 40-Gb/s/pin single-ended PAM-4 transceiver for GDDR7. LV-POD interface that separates the internal voltage from the channel supply voltage (VDDQL) is used to reduce channel power consumption. Direct 4-tap decision feedback equalizer (DFE) with timing calibrated reset-less slicer at receiver (RX) and asymmetric bidirectional T-coil are employed to achieve the highest data-rate among the state-of-the-art DRAM I/Os. The prototype chip is fabricated in mimicked 10-nm class DRAM process using 28-nm CMOS. At sub-1V VDDQL, measured TX common eye window is 0.31UI. Measured RX shmoo has total of 162 pass ticks, each tick with the size of 5mV * 1ps and BER under 10-6. The total energy efficiency of 2.02pJ/b was achieved.

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用于GDDR7应用的40gb /s/引脚低压POD单端PAM-4收发器，带定时校准无复位切片器和双向t型线圈

本文介绍了一种用于GDDR7的40gb /s/引脚单端PAM-4收发器。采用LV-POD接口，将内部电压与通道供电电压(VDDQL)分离，降低通道功耗。采用直接四分路决策反馈均衡器(DFE)，在接收器(RX)处具有定时校准的无复位切片器和非对称双向t型线圈，以实现最先进的DRAM I/ o中最高的数据速率。该原型芯片采用28纳米CMOS，采用模拟10纳米级DRAM工艺制造。在低于1v的VDDQL下，测量到的TX共眼窗为0.31UI。测量的RX shmoo共有162个通针，每个通针的尺寸为5mV * 1ps，误码率在10-6以下。总能源效率达到2.02pJ/b。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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