A 60 GHz-band S/H CMOS IC for Direct RF Undersampling Receiver

Abstract

In this paper, a 60 GHz-band Sample and Hold (S/H) IC has been developed for a direct RF undersampling receiver. In millimeter-wave wireless systems such as IEEE 802.11ad, broadband characteristic (e.g. channel bandwidth of 2 GHz) is required. In this case, the minimum sampling frequency becomes 4 GHz and output buffer amplifier should have at least 2 GHz bandwidth. This S/H-IC can sample 60 GHz RF signal by 4 GHz clock and it works as a 30th order undersampling receiver. Since the parasitic capacitance of FET used in the 2 GHz bandwidth output buffer amplifier is almost same value as the hold capacitor, the hold capacitor can be removed in our design. This S/H-IC has been fabricated in a 65nm CMOS process. The fabricated IC together with 4 GHz ADC shows SNR of 20.2 dB (channel bandwidth of 2 GHz) and EVM of less than 5.5% for 64QAM.