Horizontal microcode compaction for programmable systolic accelerators

Abstract

This paper addresses the problem of compacting microcode for complex systolic systems used as accelerators for traditional computers. For this sort of system, the purpose is to have a low-level programming paradigm that is simple enough for those users that are not completely aware of hardware details. The microcode should be issued from a high-level language application developed on the host processor. The paper introduces an effective technique to structure the microcode into elementary primitives and a simple compaction algorithm to shorten the microcode program. This compaction strategy has been tested on a real machine to implement a neural-network algorithm and some results are reported.