Mixed-signal verification methods for multi-power mixed-signal System-on-Chip (SoC) design

Abstract

Mixed-signal design becomes more and more popular nowadays because designers are required to quickly integrate IPs, control blocks, functional blocks, and analog modules together and run through the design flow to tape out in short time. Given that the latest designs are becoming more and more complex, the increasing physical effects in advanced process nodes, and request for shorter time to market, a fast and accurate design flow will be critical to ensure the success of the project. This paper will briefly describe various mixed signal verification methods used at Freescale Kinetis MCU which include behavior modeling, AMS validation, connectivity verification, mixed-signal Verification IP (VIP), multi-power verification, SoC transistor level simulation and mixed signal functional coverage. Engineering results are discussed to demonstrate the effectiveness of those methods.