Optimum wordlength determination of 8/spl times/8 IDCT architectures conforming to the IEEE standard specifications

Abstract

Optimum wordlengths for implementing an 8/spl times/8 IDCT (inverse discrete cosine transform) algorithm have been determined for minimizing the hardware implementation cost while satisfying the IEEE standard specifications. Three different implementation architectures, which are based on the multiplier-adder, distributed arithmetic, and scaled distributed arithmetic, are used for the optimization. The fixed-point optimization utility that automatically generates the fixed-point simulation model of a floating-point C program has been used. The optimization results show that the internal wordlength can be reduced substantially when compared with the previously known IDCT implementations.