A novel approach for precise characterization of long distance mismatch of CMOS-devices

Abstract

A new test structure is presented for the characterization of long distance mismatch of CMOS devices. A single circuit is used to characterize both transistors and resistors. High resolution is achieved by applying a four-terminal method with regulated reference potential to compensate for parasitic resistance effects. Measured data are presented for different CMOS processes to demonstrate the performance of this approach. In particular, the long distance matching behavior is compared to that of neighboring devices and examples for linear and nonlinear distance dependencies are shown.