{"title":"Mask topologies- a means to minimizing sensitivity to clock jitter in higher-order continuous-time sigma-delta modulators","authors":"P. Bénabès, I. Kale","doi":"10.1109/IMTC.2003.1208160","DOIUrl":null,"url":null,"abstract":"A A ? : This paper proposes and reports on results of a novel method that highly reduces the undesirable effects of clock jitter and makes the use of higher-order continuoustime sigma-delta modulators a reality thereby paving the way to the possibility of Sigma-Delta modulators operating at GHz frequencies with reduced power consumption and much simplified implementation complexities compared to their Discrete-Time Counterparts. The novel technique reported in this paper is primarily dependent on the use of HRZpulseprofiles on the feed-back DAC and the use of the MASH architecture, with a fast and accurate sample and hold circuit behveen eachfirst order stage.","PeriodicalId":135321,"journal":{"name":"Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 20th IEEE Instrumentation Technology Conference (Cat. No.03CH37412)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMTC.2003.1208160","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A A ? : This paper proposes and reports on results of a novel method that highly reduces the undesirable effects of clock jitter and makes the use of higher-order continuoustime sigma-delta modulators a reality thereby paving the way to the possibility of Sigma-Delta modulators operating at GHz frequencies with reduced power consumption and much simplified implementation complexities compared to their Discrete-Time Counterparts. The novel technique reported in this paper is primarily dependent on the use of HRZpulseprofiles on the feed-back DAC and the use of the MASH architecture, with a fast and accurate sample and hold circuit behveen eachfirst order stage.
A A ?本文提出并报告了一种新方法的结果,该方法大大减少了时钟抖动的不良影响,并使高阶连续时间sigma-delta调制器的使用成为现实,从而为sigma-delta调制器在GHz频率下工作的可能性铺平了道路,与离散时间调制器相比,其功耗降低,实现复杂性大大简化。本文报道的新技术主要依赖于在反馈DAC上使用HRZpulseprofiles和使用MASH架构,在每个一阶级之间具有快速准确的采样和保持电路。