P. Garda, A. Reichart, H. Rodriguez, F. Devos, B. Zavidovique
{"title":"Yet another mesh array smart sensor?","authors":"P. Garda, A. Reichart, H. Rodriguez, F. Devos, B. Zavidovique","doi":"10.1109/ICPR.1988.28383","DOIUrl":null,"url":null,"abstract":"Describes the architecture of a mesh array smart sensor, in close relation with the algorithms to be carried out by it. On the one hand, a monolithic implementation of the mesh array is a logical consequence of its design requirements within the framework of full custom integration. On the other hand, today's implementations are limited to Boolean picture processing and binary picture memorization if sensible size pictures are to be handled. Nevertheless, the validity of these choices is confirmed by a 50-mm/sup 2/ area (60*60PE) chip which has been laid out in a 2- mu m two-metal CMOS technology.<<ETX>>","PeriodicalId":314236,"journal":{"name":"[1988 Proceedings] 9th International Conference on Pattern Recognition","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-11-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"[1988 Proceedings] 9th International Conference on Pattern Recognition","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICPR.1988.28383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 10
Abstract
Describes the architecture of a mesh array smart sensor, in close relation with the algorithms to be carried out by it. On the one hand, a monolithic implementation of the mesh array is a logical consequence of its design requirements within the framework of full custom integration. On the other hand, today's implementations are limited to Boolean picture processing and binary picture memorization if sensible size pictures are to be handled. Nevertheless, the validity of these choices is confirmed by a 50-mm/sup 2/ area (60*60PE) chip which has been laid out in a 2- mu m two-metal CMOS technology.<>