Low-latency VLSI architecture of a 3-input floating-point adder

Abstract

In this paper, we present the design and the implementation of a 3-input IEEE 754-compliant floating-point adder. 3 level pipeline stages are used in order to distribute the critical paths and to maximize the operating frequency. The design is customizable to support various floating-point formats, including the standard single precision and double precision formats. The proposed design with the single precision, 32-bit floating-point format consumes 97207 mum square area and has an operating frequency of 420 MHz in a 0.18-mum process.