Dual Power Gating 8-Transistor SRAM Design For Low Power Applications

Abstract

As technology advances, manufacturers demand memory with low energy, high performance, and fast response SRAM (Static Random Access Memory). SRAM is a type of variable semiconductor memory that stores the binary logic digits '1' and '0'. The energy consumption of the circuit decreases as the voltage operation of the SRAM decreases, but the circuit's stability and performance suffer as the supply voltage decreases. Lower VDD increases SRAM cell latency while decreasing SRAM speed. Therefore, the study focuses on designing and implementing 6T and 8T SRAM circuits by comparing and evaluating hysteresis, energy, and margin parameters. The 6T SRAM is gated in both footer and header to save more energy. However, this low energy 6T SRAM has a small read margin. Leveraging high read margin characteristics of 8T SRAM, this paper does power gating on this type of 8T SRAM cell. By doing so, the proposed power gated 8T SRAM cell also saves energy but only keeps a high read margin. This simulation shows the leakage energy saving of the proposed 8T SRAM is up to 48% compared to that of 6T SRAM. The simulation result is performed in 130nm technology.