Hardware Architectures for Adaptive Background Modelling

Abstract

In this paper we present a hardware architecture for adaptive background modelling. Adaptive background models are used in a variety of computer vision applications, ranging from traffic monitoring to biometric identification. We report (a) a design for an adaptive background modelling algorithm; (b) implementation of the algorithm on an FPGA device; and (c) performance evaluation for our hardware architecture. One of our designs, running on a Xilinx XC2V1000 FPGA at 81 MHz, can process VGA quality 640times480 pixel frames at 132 frames per second using 291 slices and a single memory bank.