A Technique for Electrical Error Localization with Learning Methods During Post-silicon Debugging

Abstract

Error localization is a challenging step in the process of post-silicon validation owing to modern design complexity. This is exacerbated by the limited visibility of internal signals at the post-silicon validation stage. Incorporated design-for-debug features and off-line techniques assist in system-level error localization for processor based systems. However, for general SoCs and special purpose IPs, error localization at the netlist level is a challenging problem. This paper proposes a machine learning based error localization methodology during the debug step. Using limited trace data, unknown signal states are discovered with the help of cluster formation by utilizing k-nearest neighbors algorithm. These clusters assist in enhancing the internal signal state visibility to the maximum extent. We derive features from the enhanced debug data set to understand the nature of the injected bug and the erroneous flip-flop responses, which are then utilized to achieve spatial error localization.