Optimization of QDR SRAM Controller in Network Processor

Abstract

This paper presents a new architecture of shared QDR SRAM controller in the parallel processing of network processor to make the SRAM controller suitable for higher bandwidth and higher speed network communication. With line rate close to dozens of gigabit per second (Gbps), various bottlenecks related with speed, bandwidth and interface must be addressed. The arbitration mechanism is ameliorated so that simultaneous read and write operation to the memory can be executed, and a tag architecture is adopted to keep the special sequence of the SRAM reference. Thus, the bandwidth of the QDR SRAM is highly utilized.