A suite of microarchitectures for evaluating microcode compilers for other than for ISA interpretation

Abstract

This note describes a suite of microarchitectures that has been developed for evaluating microcode compilers. These architectures are not especially appropriate for the interpretation of "normal" instruction set architectures owing primarily to the lack of efficient facilities for buffering and decoding ISA level instructions. Also, a single-level, nonpartitioned control store organization is used that may not be the optimal choice for the architectures in this family.