FPGA implementation of complex-valued QR decomposition

Abstract

This paper presents a hardware architecture for the QR decomposition (QRD) of a complex-valued matrix based on Modified Gram-Schmidt (MGS) algorithm. A high throughput iterative-pipelined design is implemented, which achieves similar performance of a fully parallel-pipelined design, with a significant reduction in hardware usage. For a fixed-point Field Programmable Gate Array (FPGA) implementation optimized to decompose a 4 × 4 complex-valued matrix, an 18.6% reduction in resources utilization is achieved, compared to the fully parallel-pipelined design. Extending the proposed architecture to decompose larger matrices is straight forward, and in such cases more savings with respect to resources utilization can be attained.