SPICE compact modeling of PD-SOI CMOS devices

Abstract

This paper presents PD-SOI SPICE, which is based on compact BiCMOS charge-control models and includes second-order effects, electron and lattice temperatures, for circuit simulation of low-voltage CMOS circuits using deep-submicron partially-depleted (PD) SOI CMOS devices. This PD-SOI SPICE performs transient simulation of the write-access critical path in an SRAM composed of 42 PD SOI CMOS devices without convergence problems, which are commonly encountered while modeling PD devices due to kink effects.