8-Bit gray-scale DTCNN implementation over an FPGA for Robot Guiding algorithm

Abstract

This paper presents the application of an 8-bit Field Programmable Gate Array (FPGA) implementation of a Discrete Time Cellular Neural Network (DTCNN) suitable for small image gray-scale pre-processing (simple operations with high computational burden). It uses Split & Shift techniques to have a 12 × 12 grid. Reduced grid is necessary because of windowing process is added to process bigger images (NIOSII and peripherical elements occupation consume 4000 logic elements (LE) approximately). The implementation over the FPGA uses I2C interfece to communicate with Lego Mindstorm Device.