A Re-configurable 0.5V to 1.2V, 10MS/s to 100MS/s, Low-Power 10b 0.13um CMOS Pipeline ADC

Abstract

This work describes a re-configurable 0.5 V to 1.2 V, 10 MS/s to 100 MS/s, 10 b two-step pipeline ADC. The prototype ADC in a 0.13 um CMOS process demonstrates the measured DNL and INL within 0.35 LSB and 0.49 LSB, respectively. The ADC with an active die area of 0.98 mm2 shows the maximum SNDR and SFDR of 56.0 dB and 69.6 dB, respectively, and a power consumption of 19.2 mW at a nominal condition of 0.8 V and 60 MS/s.