Y. Gaidhani, Ashutosh Bagade, Monica Kalbande, Archana Kishorrao Vaidya
{"title":"Design of Universal Set of CMOS Gates using Multiple Valued Logic","authors":"Y. Gaidhani, Ashutosh Bagade, Monica Kalbande, Archana Kishorrao Vaidya","doi":"10.1109/ICETEMS56252.2022.10093527","DOIUrl":null,"url":null,"abstract":"The design and implementation of digital circuits are performed in the binary logic switching algebra. The binary logic switching algebra is used to design and build digital circuits. We are developing a generic collection of gates for use in the synthesis and simplification of digital MV Logic circuits. Using digital circuits with multiple-valued logic, we can reduce the number of connections. MVL digital circuits can be designed by expanding the representation domain from the binary level (N=2) switching algebra to N > 2 levels. The implementation of an MVL digital circuit uses universal sets of MVL CMOS gates. The design and implementation of a universal set of CMOS gates are the topics of this work. In this paper we are dealing with the design and implementation of a universal set of CMOS gates, which includes extended AND operators: eANDl, eAND2,eAND3, Maximum operator and Successor operators for designing of any MVL digital circuits. Implemented circuits gives the proper functionality of the MVL combinational and sequential circuit design. In this MVL digital circuit uses voltage mode for operation having different range of voltages.","PeriodicalId":170905,"journal":{"name":"2022 International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2022-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2022 International Conference on Emerging Trends in Engineering and Medical Sciences (ICETEMS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICETEMS56252.2022.10093527","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The design and implementation of digital circuits are performed in the binary logic switching algebra. The binary logic switching algebra is used to design and build digital circuits. We are developing a generic collection of gates for use in the synthesis and simplification of digital MV Logic circuits. Using digital circuits with multiple-valued logic, we can reduce the number of connections. MVL digital circuits can be designed by expanding the representation domain from the binary level (N=2) switching algebra to N > 2 levels. The implementation of an MVL digital circuit uses universal sets of MVL CMOS gates. The design and implementation of a universal set of CMOS gates are the topics of this work. In this paper we are dealing with the design and implementation of a universal set of CMOS gates, which includes extended AND operators: eANDl, eAND2,eAND3, Maximum operator and Successor operators for designing of any MVL digital circuits. Implemented circuits gives the proper functionality of the MVL combinational and sequential circuit design. In this MVL digital circuit uses voltage mode for operation having different range of voltages.