Design of Universal Set of CMOS Gates using Multiple Valued Logic

Y. Gaidhani, Ashutosh Bagade, Monica Kalbande, Archana Kishorrao Vaidya
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Abstract

The design and implementation of digital circuits are performed in the binary logic switching algebra. The binary logic switching algebra is used to design and build digital circuits. We are developing a generic collection of gates for use in the synthesis and simplification of digital MV Logic circuits. Using digital circuits with multiple-valued logic, we can reduce the number of connections. MVL digital circuits can be designed by expanding the representation domain from the binary level (N=2) switching algebra to N > 2 levels. The implementation of an MVL digital circuit uses universal sets of MVL CMOS gates. The design and implementation of a universal set of CMOS gates are the topics of this work. In this paper we are dealing with the design and implementation of a universal set of CMOS gates, which includes extended AND operators: eANDl, eAND2,eAND3, Maximum operator and Successor operators for designing of any MVL digital circuits. Implemented circuits gives the proper functionality of the MVL combinational and sequential circuit design. In this MVL digital circuit uses voltage mode for operation having different range of voltages.
基于多值逻辑的通用CMOS门设计
数字电路的设计和实现是在二进制逻辑开关代数中进行的。利用二进制逻辑开关代数来设计和构建数字电路。我们正在开发一种通用的门集合,用于数字中压逻辑电路的合成和简化。使用带有多值逻辑的数字电路,我们可以减少连接的数量。将二进制电平(N=2)交换代数的表示域扩展到N > 2电平,可以设计MVL数字电路。MVL数字电路的实现使用通用的MVL CMOS门。设计和实现一套通用的CMOS门是本工作的主题。在本文中,我们讨论了一套通用的CMOS门的设计和实现,其中包括扩展和运算符:eand1, eAND2,eAND3,最大运算符和后继运算符,用于设计任何MVL数字电路。实现电路给出了MVL组合和顺序电路设计的适当功能。在该MVL数字电路中,采用电压模式进行具有不同电压范围的操作。
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